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NVIDIA is gearing up to end 32-bit OS support



 
 
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  #1  
Old December 26th 17, 07:50 AM posted to alt.comp.hardware.pc-homebuilt,alt.windows7.general,alt.comp.os.windows-10,alt.os.linux.ubuntu
Paul[_26_]
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Posts: 655
Default NVIDIA is gearing up to end 32-bit OS support

The Natural Philosopher wrote:
On 25/12/17 18:17, Mark Lloyd wrote:
On 12/25/2017 12:01 PM, The Natural Philosopher wrote:

[snip]

In the end it was all about address space.


Address space does not depend on data word size, although the address
size is usually* a multiple of the data word size.

* not always, there is the 8086/8088 where the data size is 16 bits,
and the address size is 20 bits.


8086 was a 20 bit computer

Not a 32 bit or a 16 bit

Since you have to do address arithmetic, the size of the registers
dictates the adfess space irrsepective of whether they are used fpor
addressing or nott.

a z80 is a 16 bit computer, address space wise, and had 16 bit registers.

The anomlaies between address space and data bus size were resolved in
the 32 bit systems


8086 is a 16 bit processor.

*Something* must be used, to determine the "single point specification"
for a processor. Processors have a multiplicity of dimensions
that could be used, and the address bus is not one of them. The
Pentium 4 has a 36 bit address bus, and we do not describe
a Pentium 4 as being a 36 bit processor. Not even close.

https://en.wikipedia.org/wiki/8086

On the package pinout diagram, I see a muxed AD bus, giving
16 bits of data bus, plus additional address only bits giving
a total of 20 address bits (during address cycles). These
details are immaterial to dimensionality. I can even have
an 8 bit data bus on a 16 bit processor, to save pins, but
it would still be a 16 bit processor because it's the
plumbing inside that counts.

http://www.cpu-world.com/CPUs/8086/

8086

* 16-bit microprocessor ===
* 16-bit data bus
* Up to 10 MHz
* 1 MB RAM
* 64K I/O ports

40-pin DIP
56-pin QFP
44-pin PLCC

And from the Wikipedia article, it's a segmented processor.

"The maximum linear address space is limited to 64 KB,
simply because internal address/index registers are
only 16 bits wide. Programming over 64 KB memory boundaries
involves adjusting the segment registers"

That is definitely *not* a 20 bit processor. Address calculations
are limited to 16 bits, then you have to do some monkey
business with a segment.

The machines we built at work were like that, using
an entirely different processor and memory management
unit (a discrete MMU on a separate PCB). And when you
wrote programs, you had to be aware of segments in your
architecture. You couldn't really read the HLL code without
comments, to understand what was going on, because
of the hardware details.

I also worked on the 8048 (8748 EPROM version) as a student,
and for a student project it was pure misery. That damn thing
had 1K pages for code space, and you had to "jump"
off one page to get to the next. However, the assembler
had *no* provision for automatic management, and every
time you assembled code, you had to go back through the
code and *manually* insert all the necessary page jumping
stuff (even for a linear code sequence, the processor would
not jump to the next page on its own). It was pure misery,
and a testament to the need for a high level language
to hide the details, to escape from such drudgery. The 8048
would be an 8 bit processor, but I would instead describe
it with a profanity for a dimension.

Paul
  #2  
Old December 27th 17, 08:03 PM posted to alt.comp.hardware.pc-homebuilt,alt.windows7.general,alt.comp.os.windows-10,alt.os.linux.ubuntu
Richard Kettlewell[_2_]
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Posts: 5
Default NVIDIA is gearing up to end 32-bit OS support

Wolf K writes:
On 2017-12-26 11:55, Mark Lloyd wrote:
On 12/26/2017 01:50 AM, Paul wrote:
8086 is a 16 bit processor.

*Something* must be used, to determine the "single point specification"
for a processor. Processors have a multiplicity of dimensions
that could be used, and the address bus is not one of them. The
Pentium 4 has a 36 bit address bus, and we do not describe
a Pentium 4 as being a 36 bit processor. Not even close.


The data bus is still 32 bit.


Yes, and that AFAIK is why why we call it a 32-bit CPU.


Almost all CPUs sold under the Pentium brand had a 64 bit data bus[1],
but calling them 64-bit CPUs would have got you a very strange look.

[1] http://www.pcguide.com/ref/cpu/arch/extDataSize-c.html

Only when an x86 variant with 64-bit general-purpose registers appeared
(amd64) did anyone start calling them 64-bit CPUs.

--
https://www.greenend.org.uk/rjk/
  #3  
Old December 27th 17, 11:38 PM posted to alt.comp.hardware.pc-homebuilt,alt.windows7.general,alt.comp.os.windows-10,alt.os.linux.ubuntu
Mark Lloyd[_6_]
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Posts: 29
Default NVIDIA is gearing up to end 32-bit OS support

On 12/27/2017 02:03 PM, Richard Kettlewell wrote:

[snip]

Only when an x86 variant with 64-bit general-purpose registers appeared
(amd64) did anyone start calling them 64-bit CPUs.


OK. Base it on general-purpose registers. Not ADDRESS bus.

BTW, in one of my first microprocessor classes, a student asked the
teacher what a "bus" is. The teacher showed a sense of humor by saying
"a big long thing with 20 or 30 people on it".

--
Mark Lloyd
http://notstupid.us/

The Pope has just declared that Jesus is now an infinitly long tube of
white paste.
  #4  
Old December 29th 17, 01:35 AM posted to alt.comp.hardware.pc-homebuilt,alt.windows7.general,alt.comp.os.windows-10,alt.os.linux.ubuntu
Brian Gregory
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Posts: 10
Default NVIDIA is gearing up to end 32-bit OS support

On 26/12/2017 16:55, Mark Lloyd wrote:
On 12/26/2017 01:50 AM, Paul wrote:

[snip]

8086 is a 16 bit processor.

*Something* must be used, to determine the "single point specification"
for a processor. Processors have a multiplicity of dimensions
that could be used, and the address bus is not one of them. The
Pentium 4 has a 36 bit address bus, and we do not describe
a Pentium 4 as being a 36 bit processor. Not even close.


The data bus is still 32 bit.


The external data bus that connects to the RAM is 64 bits on the Pentium 4.

--

Brian Gregory (in the UK).
To email me please remove all the letter vee from my email address.
  #5  
Old December 29th 17, 05:25 AM posted to alt.comp.hardware.pc-homebuilt,alt.windows7.general,alt.comp.os.windows-10,alt.os.linux.ubuntu
Paul[_26_]
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Posts: 655
Default NVIDIA is gearing up to end 32-bit OS support

Brian Gregory wrote:
On 26/12/2017 16:55, Mark Lloyd wrote:
On 12/26/2017 01:50 AM, Paul wrote:

[snip]

8086 is a 16 bit processor.

*Something* must be used, to determine the "single point specification"
for a processor. Processors have a multiplicity of dimensions
that could be used, and the address bus is not one of them. The
Pentium 4 has a 36 bit address bus, and we do not describe
a Pentium 4 as being a 36 bit processor. Not even close.


The data bus is still 32 bit.


The external data bus that connects to the RAM is 64 bits on the Pentium 4.


There is more to it than that.

You can connect two Netburst processors to the same bus, and
it supports cache coherency. There's a 5 bit request field,
transferred in two phases (total ten bits), which declares
the transaction type. Some of the operations on the bus would
be address-only for snooping purposes.

Sure, the 64-bit data bus goes to the Northbridge, and from
there to single or dual channel RAM. What's missing, is the
documentation :-( It would seem, anything which travels
only between two Intel chips... doesn't need to be documented
in any useful way. I can't find any documentation that
allows me to trace how byte lane qualification is done.
DIMMs are byte-selectable. But no signal is apparent on
the Netburst FSB. The Netburst has a qualifier per 16 bits,
which doesn't seem to be a good match for making 8 bit
byte lanes on a DIMM.

As far as I know, that FSB has a cache line orientation.
The "netburst" represents a whole cache line, which becomes
a four cycle burst (for example) at the DIMM. The larger the
cache line in the architecture, the longer the DIMM burst,
and the more efficient it is. If you insert just one DIMM
in the motherboard, the burst size is eight transfers. If you
insert two DIMMs, the burst size becomes four transfers on each.
That's the basic principle. (When you have a quad channel
modern motherboard, that's when this idea seems to break
down. It's not clear that a quad channel motherboard actually
uses all four channels at the same time. The benchmarks don't
look all that good.)

There has to be some sort of alternate representation to
address things on the Southbridge. Addressing smaller
quantities would really help, for Southbridge register access.
But without documentation, who knows how that works.

*******

This motherboard is an example of Asus using a Northbridge
intended for consumer motherboards, as a dual socket "workstation/server"
class motherboard. This board was a favorite, over on 2cpu.com
forums at one time. (I have the consumer version with an 875P
and just one processor. Most normal 875P boards have one socket.
I don't think Intel would be all that happy with this development,
because it broke the "class structure". Score one for Asus.)

https://www.asus.com/ca-en/Commercia...s/PCDL_Deluxe/

Xeon Xeon
| |
+---+----+ --- quad pumped netburst FSB, cache coherent
|
875P ---- dual_channel_RAM
|
SB

Snoop traffic on such a (multi-socket) bus, is a waste of bus bandwidth.
This is why processors which consist of two silicon dies, like
the Q6600,

http://cdn.overclock.net/3/37/376a75...tach92726.jpeg

they have interconnect similar to that motherboard.
The two silicon dies have their FSBs joined, and snoop traffic
travels between the two processor caches. The end result is,
the four processor cores run at about 88% efficiency when
you benchmark multithreaded code. When you put all cores
on the same silicon die, the efficiency jumps to 100%
(the snooping still happens, but you can do a better
implementation).

That thing isn't as much a bus, as it's a "plumbing experience" :-)
Because at least some things happen in bursts, the transaction size
is a lot bigger than 64 bits. The bit width, doesn't give any
indication of what it's doing. Or what it's capable of doing.

Paul

  #6  
Old December 29th 17, 07:18 AM posted to alt.comp.hardware.pc-homebuilt,alt.windows7.general,alt.comp.os.windows-10,alt.os.linux.ubuntu
Anssi Saari
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Posts: 123
Default NVIDIA is gearing up to end 32-bit OS support

Paul writes:

Brian Gregory wrote:


The external data bus that connects to the RAM is 64 bits on the Pentium 4.


There is more to it than that.


For sure. But in fact, the original Pentium from 1993 already had the
external 64-bit data bus. Problem was, registers were only 32-bits wide
and there were no instructions to do 64-bits reads or writes. Unless you
used the FPU and later MMX and its successors.
  #7  
Old December 29th 17, 03:28 PM posted to alt.comp.hardware.pc-homebuilt,alt.windows7.general,alt.comp.os.windows-10,alt.os.linux.ubuntu
Brian Gregory
external usenet poster
 
Posts: 10
Default NVIDIA is gearing up to end 32-bit OS support

On 29/12/2017 07:18, Anssi Saari wrote:
Paul writes:

Brian Gregory wrote:


The external data bus that connects to the RAM is 64 bits on the Pentium 4.


There is more to it than that.


For sure. But in fact, the original Pentium from 1993 already had the
external 64-bit data bus. Problem was, registers were only 32-bits wide
and there were no instructions to do 64-bits reads or writes. Unless you
used the FPU and later MMX and its successors.


That's a problem only if you pointlessly insist on everything being the
same bit width.

As you know the extra width isn't wasted because most of the
transactions over the 64 bit bus are filling sections of the caches in
the CPU and they use the full width at full speed.

Many processors have features that different bit widths.

--

Brian Gregory (in the UK).
To email me please remove all the letter vee from my email address.
 




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