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why does increasing the fsb speed, increase the memory bus?



 
 
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  #1  
Old September 6th 04, 01:22 PM
Anon
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Default why does increasing the fsb speed, increase the memory bus?

why does increasing the fsb speed, increase the memory bus?

can the memory bus be overclocked without overclocking the fsb?

if so, then does the memory bus have its own clock?
and why would increasing the fsb clock increase the memory bus?

if not, (i.i, if you can only increase the mem bus by increasing the
fsb) then is the memory bus a multiple or a fraction of the speed - or
either?

why does fsb set the clock for everything and the memory bus doesn't?

thanks
  #2  
Old September 6th 04, 05:54 PM
rms
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why does increasing the fsb speed, increase the memory bus?

The clocks for the two busses were tied together in older, simpler
designs. Only in newer designs has it been possible to have some degree of
independence between the two.

can the memory bus be overclocked without overclocking the fsb?


Yes, you can do this on most motherboards, like the Abit NF7, but since
memory designs are generally less tolerant of high busspeeds than cpus,
generally you run them the same speed or have the memory bus run at some
fraction of the fsb. There are inefficiencies that crop up when running at
some fraction other than 1:1, so this is preferred.

if so, then does the memory bus have its own clock?


On simpler designs like AthlonXP chipsets, the two are tied together,
though you can alter the ratio between them. On newer designs like the
Athlon64, they are completely independent.

and why would increasing the fsb clock increase the memory bus?


Explained above.

why does fsb set the clock for everything and the memory bus doesn't?


In the far past it was common to have the memory data bus connected to
the same pins as the cpu input/output data pins (fsb). Now they are usually
separate, for increased performance.

rms



thanks



  #3  
Old September 7th 04, 12:04 AM
Anon
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"rms" wrote in message . com...
why does increasing the fsb speed, increase the memory bus?


The clocks for the two busses were tied together in older, simpler
designs. Only in newer designs has it been possible to have some degree of
independence between the two.

snip
if so, then does the memory bus have its own clock?


On simpler designs like AthlonXP chipsets, the two are tied together,
though you can alter the ratio between them. On newer designs like the
Athlon64, they are completely independent.

snip
why does fsb set the clock for everything and the memory bus doesn't?


In the far past it was common to have the memory data bus connected to
the same pins as the cpu input/output data pins (fsb). Now they are usually
separate, for increased performance.

rms


What's the name of the architecture in the old design(like Athlon XP),
and the architectural name of the new design(like Athlon 64)?

What books discuss these things (the old architecture - including its
name, the new architecture? (bigelow,mueller,minasi?)
And where are the even more technical things such as the memory
databus being connected to the same pins, where is that discussed? (do
I have to look at electronic schematics or is there a watered down
thing)?

the most that online resources seem to say is that the athlon 64 has
no fsb at all.

I checked the AMD website for information on the AMD Athlon 64
chipset, but it seems like the chipsets can be made by different
companies, like Via and SiS. I can't find any standards written by AMD
discussing the architecture
  #4  
Old September 7th 04, 02:50 AM
rms
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Default

What books discuss these things (the old architecture - including its
name, the new architecture?


The Pentium and athlon64 architecture is discussed at length in articles on
www.arstechnica.com You can search for more yourself.

rms


  #5  
Old September 7th 04, 07:25 AM
Wes Newell
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On Mon, 06 Sep 2004 16:04:13 -0700, Anon wrote:

What's the name of the architecture in the old design(like Athlon XP),
and the architectural name of the new design(like Athlon 64)?

There isn't a name afaik. it's just different engineering designs.

What books discuss these things (the old architecture - including its
name, the new architecture? (bigelow,mueller,minasi?)


I don't know. I don't need no stinkin book.:-)

And where are the even more technical things such as the memory
databus being connected to the same pins, where is that discussed? (do
I have to look at electronic schematics or is there a watered down
thing)?

Hey, schematics are great if you can read them.

the most that online resources seem to say is that the athlon 64 has
no fsb at all.

Only because they they changed the name to HyperTransport. it's basically
the same thing with a new name, except ram data has it own bus direct to
the cpu rather than going through the ram bus to the chipset and then from
there over the FSB to the cpu.

I checked the AMD website for information on the AMD Athlon 64
chipset, but it seems like the chipsets can be made by different
companies, like Via and SiS. I can't find any standards written by AMD
discussing the architecture


SIS shows system configurations for all their chipsets that are easy to
understand. the SIS 748 is for 32bit, and the 755's are for 64 bit. note
the differences, well there's really just one other than bus name.

http://www.sis.com/products/




--
Abit KT7-Raid (KT133) Tbred B core CPU @2400MHz (24x100FSB)
http://mysite.verizon.net/res0exft/cpu.htm
 




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