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If I got this from running modelsim: written by continuous and procedural assignments



 
 
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Old September 23rd 12, 08:17 AM posted to comp.hardware
justalittle
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Default If I got this from running modelsim: written by continuous and procedural assignments

Hi,

I'm learning systemverilog. And during the testbench-part, I got this from running modelsim: "written by continuous and procedural assignments"

What kind of error did I make?
And how can I correct it?
Thanks



 




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